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// pwm_gen.vtimescale 1ns / 1psmodule pwm_gen( input clk, input rst, input en, input [15:0] period, input [15:0] h_time, output reg pwm);reg [31:0] CNT;always @(posedge clk or negedge rst) begin if (!rst) { CNT <= 0; } else if (CNT >= period-1 || en == 0) { CNT <= 0; } else { CNT <= CNT + 1'b1; }endalways @(posedge clk or negedge rst) begin if (!rst) { pwm <= 0; } else begin if (en == 0) { pwm <= 0; } else begin if (CNT <= h_time-1) { pwm <= 1; } else { pwm <= 0; } end endendendmodule ??????PWM????????????????
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